The semiconductor industry has continually improved the processing capabilities and power consumption of integrated circuits (ICs) by shrinking the minimum feature size. However, in recent years, process limitations have made it difficult to continue shrinking the minimum feature size. The vertical integration of two-dimensional (2D) ICs into three-dimensional (3D) ICs has emerged as a potential approach to improving processing capabilities and power consumption of ICs. By vertically integrating 2D ICs into 3D ICs, footprints are reduced and metal interconnect distance is shortened, thereby improving processing capabilities and reducing power consumption. Wafer-to-wafer bonding technology has been developed to bond two wafers together, such that the 2D ICs in the respective wafers can be integrated into 3D ICs.